1. Field
The following description relates to a level shifter. The following description also relates to a multi power supply type level shifter configured as a two-stage level shifter, each stage having four MOS transistors to constantly output voltages at a constant level regardless of a power-on sequence.
2. Description of Related Art
In order for general memory circuits or various integrated circuit (IC) circuits to operate normally, an appropriate voltage needs to be applied to the circuit. Most semiconductor integrated circuits include several circuit blocks for executing various functions, and there are various power supply voltages for driving these circuit blocks. Accordingly, the circuit blocks use a level shifter to change a voltage level in order to successfully interface between the respective circuit blocks.
For example, such a level shifter is used in a display driver IC (DDI) such as a driving IC for driving a panel of an organic light-emitting diode (OLED) or a liquid crystal diode (LCD). These ICs enable a plurality of power supplies to be sequentially supplied to the level shifter to correspond to a power-on sequence. By providing power in this manner, it allows a series of image data items to be displayed on a screen while appropriately changing a signal level.
Typically, a power supply voltage applied to the level shifter included in the IC includes a first power supply (VDDL) and a second power supply (VDDH) as power-on voltages and a third power supply (VSSH) as a ground voltage (GND). However, the ground voltage (VSSH) may not have a ‘0’ level. In an example, the VSSH has a ‘minus (−)’ value, and the first power supply (VDDL) has a ‘0’ value. In this example, the second power supply (VDDH) has a power supply voltage that is higher than the first and third power supplies.
The power supply voltages are applied in a two-stage level shifter in a predetermined sequence. In the sequence, the power supply voltages are applied in a specific sequence, such as of VDDL->VSSH->VDDH.
However, sometimes an error may occur the power supply voltages are not applied in the predetermined sequence due to a fault in system design or unintentional factors caused by external noise at the time of system operation.
Thus, there are issues that levels of output voltages of the level shifter are not constant and various circuit devices constituting the level shifter are potentially physically damaged by short-circuit currents generated by improperly activated operations of MOS transistors.
A situation where issues result from a change in a supply sequence of the power supply voltages is described with reference to FIG. 1. FIG. 1 is an example of a circuit configuration diagram showing a level shifter having a multi power supply structure.
In the circuit configuration diagram described below, a metal-oxide semiconductor (MOS) transistor is referred to as a PM or NM depending on whether the MOS transistor is a P-type or N-type. A MOS transistor is a transistor used for amplifying or switching electronic signals by providing a conducting channel that includes carriers to transmit the signal. In an N-type MOS transistor, the carriers are electrons, and in a P-type MOS transistor the carriers are holes.
As shown in FIG. 1, a level shifter 10 includes a first level shifter 20 and a second level shifter 30 each having four MOS transistors. In each level shifter, two of the MOS transistors are P-type MOS transistors, and two of the MOS transistors are N-type MOS transistors. Here the level shift 10 is a two-stage level shifter.
The first level shifter 20 includes a PM 1 and a PM 2 that respectively receive an input voltage IN. The first level shifter 20 also receives an input voltage INb inverted by an inverter 2 and a NM 1 and a NM 2 that act as a latch circuit for pulling-down the input voltage IN.
Gates of the PM 1 and the PM 2 are respectively connected to the input voltage IN and the inverted input voltage IN b. The sources of the PM 1 and the PM 2 are connected to a first power supply (VDDL). Drains of the PM 1 and the PM 2 are respectively connected to a node a and a node b to be connected to the NM 1 and NM 2 as a latch circuit.
Gates and drains of the NM 1 and the NM 2 constituting a latch circuit are cross-connected between the node a and the node b. The sources of the NM 1 and the NM 2 are connected to a third power supply (VSSH). V1 and V2 represent voltage potentials of the node a and the node b. V1 and V2 are connected to the second level shifter 30.
The second level shifter 30 includes a NM 3 and a NM 4 that receive the V1 and the V2 and latch circuits PM 3 and PM 4 that act as pull-up devices.
Gates of the NM 3 and the NM 4 receive the V1 and the V2, respectively. Sources of the NM 3 and the NM 4 are connected to the third power supply (VSSH). Drains of the NM 3 and the NM 4 are respectively connected to a node c and a node d to be connected to the PM 3 and the PM 4.
Thus, gates and drains of the PM 3 and the PM 4 are cross-connected to the node c and the node d, and the sources of the PM 3 and the PM 4 are connected to the second power supply (VDDH).
A case in which the first power supply (VDDL) is not applied in such a two-stage level shifter of a multi power supply type is described as an example.
When the first power supply (VDDL) is not applied, gate potentials of the NM 1 and the NM 2 enter a ground (GND) state or a floating state of a ground (GND) level.
As a result of this situation, the PM 1 and the PM 2 that are connected to the node a and the node b are turned on. All MOSs of the first level shifter 10 are turned on in this situation, and thus current paths from the PM 1 and the PM 2 to the NM 1 and the NM 2 are formed in the first level shifter 10 that cause a short-circuit current.
Similarly, when the voltage potentials V1 and V2 of the node a and the node b become potentials for turning on the NM 3 and the NM 4, the PM 3 and the PM 4 are also turned on. Thus, current paths from the PM 3 and the PM 4 to the NM 3 and the NM 4 are formed in such a situation that generate a short-circuit current.
Additionally, the level shifter 10 includes a PM 5 and a NM 5. The PM 5 and the NM 5 serving as inverters that form an output terminal of the second level shifter 30 are also turned on by a voltage potential V4 on a node that connects the PM 4 and the NM 4. Thus, a short-circuit current flows through the NM 5 from the PM 5.
Based on the issues just discussed, the level shifter 10 potentially does not operate as designed due to an unintentional current in the level shifter 10, such as a short-circuit current. In some cases, when the amount of short-circuit current is large, various devices constituting the level shifter, that is, the MOSs themselves, are physically damaged.
Accordingly, when the level shifter 10 encounters such a situation, the output voltage level is changed in a manner contrary to the design of the level shifter 10.
Similar issues are also caused when the second power supply (VDDH) is applied before the third power supply (VSSH) is applied.
In the aforementioned level shifter 10, current flow states between the PM 5 and the NM 5 depending on a power-on sequence of the VDDL, VDDH, and VSSH are defined in Table 1, and are also illustrated with reference to FIG. 2. FIG. 2 is a diagram illustrating a generating region corresponding to a short-circuit current of the level shifter 10 shown in FIG. 1.
TABLE 1Power-on stateNode voltageVDDLVDDHVSSHV1V2V3V4OUTSCCGNDGNDP-OFFTTTYesGNDP-OGNDFFTTTYesGNDP-OP-OFFTTTYesP-OGNDP-OH/LL/HL/HH/LL/HNoP-OP-OGNDH/LL/HL/HH/LL/HNo
In Table 1, various combinations of possible power-on states for VDDL, VDDH, and VSSH are presented. The power-on states are represented by Ground (GND) or Power-On (P-O). Based on the power-on states, Table 1 presents corresponding node voltages for V1, V2, V3, V4, and OUT. The node voltages are represented by Floating (F), Transition (T), High or Low (H/L), or Low or High (L/H). The SCC column is a group of entries that indicate whether there is a short-circuit current of inverters PM 5 and NM 5, based on the other columns.
When the VDDL is applied, since the current flow is blocked, a short-circuit current is not generated. Meanwhile, when the VDDL is grounded and the VDDH or the VSSH is applied, a short-circuit current is generated between the PM 5 and the NM 5.
In approaches, in order to avoid the short-circuit current, a power supply unit in which a power-on sequence is previously determined is separately provided. However, in such an approach, a circuit configuration of the power supply unit becomes more complicated.